1. Field of the Invention
The present invention relates to a digital-to-analog converter and, more particularly, to the reduction of distortion in the output signal of a digital-to-analog converter which is fabricated as an integrated circuit (IC). The present invention is intended to eliminate the effect of a bias voltage applied to a substrate of a ladder circuit type (R-2R ladder type network) digital-to-analog converter (D/A converter).
2. Description of the Prior Art
Many D/A converters have been proposed that convert digital signals to analog signals and which are principally ladder circuits, as illustrated in the block diagram of FIG. 1. When an input digital signal consisting of bit signals A.sub.0,A.sub.1,A.sub.2, . . .,A.sub.n is applied to the circuit, each bit signal controls a corresponding switch I.sub.0,I.sub.1,I.sub.2, . . .,I.sub.n consisting of, for example, an inverter I, and a reference voltage V.sub.REF or a ground voltage is connected to an output terminal V.sub.out through the switches I.sub.0,I.sub.1,I.sub.2, . . .,I.sub.n. The ladder circuit 1 in FIG. 1 is constructed of two resistors R and 2R, connected as shown. The resistance of resistors 2R is twice that of resistors R and such a ladder circuit is called an R-2R ladder network. The combined impedance at each branch point or connection point of the ladder circuit 1, looking toward the right in FIG. 1, is equal to R, so, if each of the branches 2R are connected to a reference voltage source V.sub.REF through the switches, the output voltage V.sub.out can be written as EQU V.sub.out =V.sub.REF (A.sub.0 /2+A.sub.1 /2.sup.2 +A.sub.2 /2.sup.3 +. . .+A.sub.n /2.sup.n) (1)
As can be seen from FIG. 1 and the above equation, each bit applied to each switch contributes to the output voltage in correspondence with the order of significance for that bit. A.sub.0 is the most significant bit (MSB), and the bit A.sub.n is the least significant bit (LSB).
FIG. 2 illustrates an example of a circuit diagram of the circuit of FIG. 1. The circuit is constructed as a ladder circuit, consisting of resistors R and 2R, and inverter circuits I.sub.0,I.sub.1,I.sub.2, . . .,I.sub.n consisting of complementary MOS (metal oxide semiconductor) transistors. Each inverter circuit has an input terminal A.sub.0,A.sub.1,A.sub.2, . . .,A.sub.n, and each consists of both p-type and n-type MOS transistors, having gate electrodes connected to each other and to the respective input terminal. Drain electrodes of the p-type MOS transistor and the n-type MOS transistor are connected to each other at a connection point 0 which is connected to the respective 2R resistor. Source electrodes of the p-type MOS transistor and the n-type MOS transistor are connected respectively to reference voltage V.sub.REF and ground, respectively. The other side of each resistor 2R is linked to each connection point of series connected resistors R and the end of the ladder circuit is grounded through a resistor 2R. An input digital signal which is usually stored in a register or supplied directly from a logic circuit is applied to the D/A converter circuit and each bit is separately supplied to each input terminal A of the respective inverter circuit I. The same notation is used for each input terminal and each bit of the digital input signal (A.sub.0,A.sub.1,A.sub.2, . . .,A.sub.n). The first bit A.sub.0 (that is the MSB) is supplied to the first inverter circuit I.sub.0, and the second most significant bit A.sub.1 is supplied to the second inverter circuit I.sub.1, and so forth, and the least significant bit A.sub.n is supplied to the last switching inverter circuit I.sub.n. When the input terminals of the inverters are supplied with "0" or "1" signals corresponding to the code of the input signal, each inverter supplies, corresponding to each input signal, the reference voltage V.sub.REF or the ground voltage to the respective series resistor junction point through resistor 2R.
For example, if the input signal is 1,1,1, . . .,1, that is if all bits are "1", (A.sub.0 =A.sub.1 =A.sub.2 =. . .=A.sub.n =1, all inverters are supplied with a "1" signal, and the gate potential of all transistors is high. The p-channel type MOS transistors (p-MOS) are "off", the n-channel type MOS transistors (n-MOS) are "on" and the connection points 0 are at the ground potential. If the input signal is 0,0, . . .,0, all inverters are supplied with a "0" signal, and the gate potential of all transistors is low. The p-MOS transistors are "on", the n-MOS transistors are "off" and and the connection points 0 are at the reference voltage V.sub.REF. The output voltage V.sub.out is the accumulation or sum of the potential of each series resistor connection point according to the weight of each corresponding bit as expressed mathematically by equation (1).
FIG. 3, including FIG. 3(a) and 3(b), illustrates an example of a resistance fabricated in a semiconductor which is widely used as the resistances of the resistors in the D/A converter. FIG. 3(a) illustrates a cross-sectional view of a resistor, and FIG. 3(b) illustrates a plan view of a plurality of the resistors showing their alignment. A substrate 2 of an IC die (or chip) is made from, for example, an n-type silicon. As would be recognized by a person of skill in the art, the substrate may be of a p-type silicon or any other type semiconductor material. However, the description herein will be made with respect to an n-type silicon substrate. If another material is substituted, the needed modifications of the present invention will be possible by a person of skill in the art. The process for fabricating the resistors is known by those of skill in the art, does not relate directly to the present invention and will be explained only briefly to describe the structure of the resistor. After the fabrication of a field oxide layer 3, a P-type well 4 is formed in the substrate 2. In the P-well 4, terminal electrodes 5 are fabricated by diffusion with a very high dose of an n-type dopant. Such a very high doped region is often called an N.sup.++ region. Fabricated between the N.sup.++ regions is a region N.sup.+6 which is highly doped with n-type dopant and forms the resistor. These resistors have a strip type configuration and are arranged in parallel with each other as shown in FIG. 3(b). The resistance value of a resistor is determined by the size of the strips and the resistivity of the N.sup.+ region in accordance with EQU R=R.sub.a 1/w (2)
where R.sub.a is the sheet resistivity of the N.sup.+ region, 1 is the length of the resistor strip and w is the width of the diffusion layer. The resistors can be fabricated by photo-lithography and a selective diffusion technique for example, both fundamental, well known processes in semiconductor manufacturing.
Generally the resistance value of each resistor is fabricated as equal to R and to form resistors of 2R in the resistance network, two resistors are connected in series. Sometimes the resistance value is fabricated as equal to 2R, and resistor R is made by connecting two resistors in parallel and these two methods are the preferable ones for fabricating a precise value of R and 2R.
After the resistors 6 are fabricated, the surface of the substrate is coated with a phospho-silicate glass (PSG) layer 7 used for surface passivation. Contact windows are opened at proper positions on the PSG layer 7, and the circuit is completed by connecting these resistors using aluminum wiring 8 and 9, as shown in FIG. 3(a). In FIG. 3(b), the aluminum wiring 8 and 9, and the PSG layer 7 are not shown to clearly show the alignment of the resistor strips.
In order to integrate such a D/A converter into an IC, it is necessary to fabricate the resistors very precisely which increases the difficulty of manufacturing and decreases the yield. However, a more significant problem is that the resistance value of each resistor is varied by a bias voltage applied to the substrate of the IC which is an inevitable and inherent characteristic of a MOS device.
Usually one of the highly doped N.sup.++ regions of an n-type resistor (which is made of an n-type conductivity semiconductor), suitable for a CMOS (complementary MOS) transistor, is used to supply a bias voltage to the substrate. For example, as shown in FIG. 3(a), the substrate is biased with 5 volts through the electrode 8 and the electrode 9 is grounded. With respect to the substrate 2, the potential of the electrode 8 is zero and the potential of electrode 9 is -5 volts.
It is well known in the art that the resistivity of a channel of n-type conductivity varies as shown by curve 10 in FIG. 4, when the bias voltage is varied. This variation is due to the variation of the channel depth caused by the bias voltage. The details of this phenomena are described, for example, in Analog Integrated Circuit Design by A. B. Grebne, published in 1972 by Litton Educational Publishing Inc. The sheet resistivity of the portion of the resistor (N.sup.+ layer) closest to the electrode 8, where it is biased nearly to 0 volts with respect to the substrate 2, is low (see 11 in FIG. 4), while the sheet resistivity of the portion of the resistor closest to the electrode 9, where it is biased -5 volt wth respect to the substrate 2, is high (see 12 in FIG. 4). The sheet resistivity between the electrodes 8 and 9, varies from the low value at 11 gradually to the high value at 12, as the measurement point moves from electrode 8 to electrode 9. It is, therefore, difficult to precisely fabricate the resistors R and 2R as determined by equations (1) and (2), because they are affected by the bias voltage applied to the substrate.
A D/A converter as in FIG. 2 having a resistor network fabricated in the same IC substrate, has non-linear input-output characteristics as illustrated by curve 13 in FIG. 5. Curve 13 illustrates the characteristics of a D/A converter having an n-type conductivity resistance network. It will be understood by those of skill in the art that a D/A converter having a p-type conductivity resistance network has characteristics like curve 14 in FIG. 5. The characteristics of curves 13 and 14 are reversed with respect to each other because the p-type conductivity and n-type conductivity are performed by holes and electrons respectively. The non-linear characteristics illustrated are almost an inherent defect of an integrated circuit type D/A converters consisting of a semiconductor ladder type network and the non-linearity of the analog output signal as compared to the digital input signal is inevitable in prior art D/A converters.